The present invention is directed generally to testing digital systems, and more particularly to using scan test techniques to test the interconnecting signal lines between digital circuits employing different or non-compatible scan test architectures.
As integrated circuit technology has advanced over the past decade or so, circuit density has increased significantly. In order to test such circuitry, a variety of techniques have been advanced. One such technique enjoying a not insubstantial use at present determines nothing more than whether particular digital circuit, or system, is operable or not; e.g., a GO/NO-GO test technique. This technique requires use of "scannable" registers to be incorporated in the integrated circuit, forming the flip-flops, counters, latches, registers, and the like. The scannable register are structured to selectively operate in one of two modes: a normal mode to perform functions within the design of the circuit or system that includes the scannable register, and responsive to test signals in a test mode in which the scannable register is combined with other scannable registers to form one or more long shift registers or "scan chains" that receive test patterns. According to one version of this technique, the circuit or system tested is repeatedly placed in a pseudo-random state, allowed to execute one normal cycle, and the resultant state extracted and combined with other extracted states to form a signature that is compared to a "golden" signature developed from a known good integrated circuit or group of integrated circuits--identical to that under test. The compare provides the GO/NO-GO indication. Examples of this technique can be seen in U.S. Pat. Nos. 4,718,065. Pseudo-random scan test techniques, such as described above, may also be used for receiving predetermined test patterns make specific test determinations.
Scan test architectures, whether for pseudo-random scan testing, or for testing using predetermined test patterns, or both, are at times different; some may be more robust than others, or perform the scan test differently, thereby requiring different scan test architecture. For example, the more robust scan test methods provide for the testing to be performed "at speed" (i.e., testing is performed at the speed of the system clock used by the circuit or unit under test). Another architecture, albeit less robust than full (at speed) PRST, is that described by IEEE Standard 1149.1, promulgated by the Joint Test Action Group (JTAG), a collaborative organization comprised of major semiconductor users in Europe and North America. According to this Standard, the architecture will provide for tests that, among other things, can sample various inputs and outputs of the unit under test (external tests), as well as being able to test certain of the internal circuits of the unit under test (internal tests).
Digital systems that mix different (and at some times, non-compatible) types of scan test architectures will often require separate tests to be conducted on each of the different architectures at the cost of extra time and labor, additional signal leads and pins, and the like. The problem is exacerbated when the interconnect carrying signals between the two scan architectures is to be tested, often necessitating manual methods for such testing which is expensive in both time and labor.